Why does the JK flip-flop toggles on the 'negative edge' of its clock input when its inputs are connected to +v (i.e when j=1 , k=1)? - Quora
Flip-Flops and Latches - Northwestern Mechatronics Wiki
flipflop - Is it mandatory to include a pulse detector in order to design an edge-triggered JK Flip Flop using logic gates? - Electrical Engineering Stack Exchange